Nanotechnology and Nano electronics Engineering Department , UST at Zewail City 12578 Ahmed Zewail Street, October Gardens 6th of October City, Giza, Egypt.
10.21608/iugrc.2022.302717
Abstract
RISC-V is an open Instruction Set Architecture (ISA) that is expected to dominate the market in the next few years. It is forecasted that market will consume 62.4 billion RISC-V CPU cores by 2025. In this project a RISC-V core is physically implemented as an ASIC using Nangate Open Cell Library 45nm PDK and its performance is compared to a 45nm based Spartan 6 FPGA implementation.
El-desouky, M. (2022). RISC-V Core FPGA/ASIC Performance Comparison: A 45nm Case Study. The International Undergraduate Research Conference, 6(6), 1-3. doi: 10.21608/iugrc.2022.302717
MLA
Mohammed El-desouky. "RISC-V Core FPGA/ASIC Performance Comparison: A 45nm Case Study". The International Undergraduate Research Conference, 6, 6, 2022, 1-3. doi: 10.21608/iugrc.2022.302717
HARVARD
El-desouky, M. (2022). 'RISC-V Core FPGA/ASIC Performance Comparison: A 45nm Case Study', The International Undergraduate Research Conference, 6(6), pp. 1-3. doi: 10.21608/iugrc.2022.302717
VANCOUVER
El-desouky, M. RISC-V Core FPGA/ASIC Performance Comparison: A 45nm Case Study. The International Undergraduate Research Conference, 2022; 6(6): 1-3. doi: 10.21608/iugrc.2022.302717
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